This invention relates to a method for controlling a semiconductor processing apparatus. More particularly, the invention relates to a method for controlling a semiconductor processing apparatus which method can operate the apparatus at a high rate of operation.
Processing performance of a semiconductor processing apparatus such as an etching processing apparatus varies with time as wafer processing is repeated. When this change with time proceeds, processing shape or size of a wafer surface structure acquired by etching process change gradually and a processing size eventually falls off from a management reference value→falls out of a control limit. In other words, abnormality of a process condition (process abnormality) develops.
FIGS. 9A and 9B are explanatory views useful for explaining causes of the occurrence of process abnormality. FIG. 9A shows a processing chamber (vacuum processing chamber) under a clean state immediately after wet cleaning. FIG. 9B shows a state where deposition is developed onto an inner wall surface of the processing chamber as the wafer processing is repeated. In the drawings, reference numeral 1 denotes the processing chamber. Reference numeral 2 denotes a sample placement electrode on which a sample to be processed is placed. Reference numeral 3 denotes a sample such as a wafer. Reference numeral 4 denotes plasma that is generated inside the processing chamber. Reference numeral 5 denotes deposition developed onto the inner wall of the processing chamber.
When wafer processing is repeated and the deposition is developed onto the inner wall surface of the processing chamber as shown in FIG. 9B, the condition of the plasma changes due to interaction between the deposition and plasma generated inside the processing chamber, and the change of the plasma condition results in the change of the processing shape (processing size) of structures on the wafer.
The gradual change in the processing shape resulting from the change with time finally exceeds a control limit and induces a critical problem of performance of semiconductor devices fabricated on the wafer surface. In other words, a process abnormality as described above develops.
FIG. 10A and FIG. 10B explain a process when a process abnormality develops. FIG. 10A shows an example where the process is stopped upon the occurrence of the process abnormality. FIG. 10B shows an example that changes a processing method (recipe) of a next wafer when the process abnormality develops.
In the example that stops processing when the process abnormality develops, a processing result is diagnosed at the end of (or during) wafer processing on the basis of sensor data of the wafer process (Steps S1 and S2) as shown in FIG. 10A. Processing of the next wafer is stopped when the processing result proves abnormal (Step S6), but is conducted when it is normal (Step S3). This operation is thereafter repeated successively for each wafer (Steps S4, S5 and S7).
In the example that changes the processing method (recipe) of the next wafer when the process abnormality develops, the processing result is diagnosed at the end of (or during) the wafer processing on the basis of the detection data of the monitors (Steps S1 and S2) as shown in FIG. 10B. When the processing result proves abnormal, the processing method of the next wafer is controlled (that is, the recipe is changed) and the next wafer is processed (Steps S6 and S3). When the processing result proves normal, processing of the next wafer is conducted without changing the recipe (Step 3). This operation is thereafter repeated successively for each wafer (Steps S4, S5 and S7).